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PLL502-22 Datasheet(PDF) 5 Page - PhaseLink Corporation |
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PLL502-22 Datasheet(HTML) 5 Page - PhaseLink Corporation |
5 / 6 page Preliminary PLL502-22 384MHz – 768MHz Low Phase Noise LVDS VCXO (12 – 24MHz Crystal) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/17/01 Page 5 7. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf RL = 100 Ω CL = 10 pF (see figure) 0.2 0.7 1.0 ns OUT OUT V OD V OS 50 Ω 50 Ω OUT V DIFF R L = 100Ω C L = 10pF C L = 10pF LVDS Switching Test Circuit LVDS Levels Test Circuit LVDS Transistion Time Waveform OUT OUT OUT 0V (Differential) 0V 20% 80% 20% 80% t R t F V DIFF |
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