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PLL500-37 Datasheet(PDF) 3 Page - PhaseLink Corporation |
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PLL500-37 Datasheet(HTML) 3 Page - PhaseLink Corporation |
3 / 5 page (Preliminary) PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 3 2. AC Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Input Crystal Frequency 36 130 MHz 0.8V ~ 2.0V with 10 pF load 1.15 Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 3.7 ns Output Clock Duty Cycle Measured @ 1.4V 45 50 55 % Short Circuit Current ±50 mA 3. DC Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current, Dynamic, with Loaded Outputs IDD FXIN = 77.76MHz Output load of 15pF 7.2 9 mA Allowable output load ca- pacitance CL (Output) Standard drive up to 100MHz 15 pF Operating Voltage VDD 2.25 3.63 V Output Low Voltage at CMOS level VOLC IOL = +4mA 0.4 V Output High Voltage at CMOS level VOHC IOH = -4mA VDD – 0.4 V Output drive current For VOL<0.4V or VOH>2.4V 8 mA Short Circuit Current ±50 mA VCXO Control Voltage VCON 0 VDD V 4. Voltage Control Crystal Oscillator PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS VCXO Stabilization Time * TVCXOSTB From power valid 10 ms VCXO Tuning Range FXIN = 36 – 130MHz; XTAL C0/C1 < 250 0V ≤ VCON ≤ 3.3V 300 ppm CLK output pullability VCON=1.65V, ±1.65V ±150 ppm VCXO Tuning Characteristic 100 ppm/V Pull range linearity 5 % Power Supply Rejection PWSRR Frequency change with VDD varied +/- 10% -1 +1 ppm VCON pin input impedance 2000 k Ω VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB 45 kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. |
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