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PLL502-12SOM Datasheet(PDF) 4 Page - PhaseLink Corporation |
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PLL502-12SOM Datasheet(HTML) 4 Page - PhaseLink Corporation |
4 / 6 page Preliminary PLL502-12 96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 7/15/02 Page 4 5. Jitter and Phase Noise specification PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS at 155MHz With capacitive decoupling between VDD and GND. 9 ps Accumulated jitter RMS at 155MHz With capacitive decoupling between VDD and GND. Over 10,000 cycles. TBM ps Integrated jitter RMS at 155MHz Integrated 12 kHz to 20 MHz 3 4 ps Phase Noise relative to carrier 155MHz @10Hz offset -60 dBc/Hz Phase Noise relative to carrier 155MHz @100Hz offset -90 dBc/Hz Phase Noise relative to carrier 155MHz @1kHz offset -112 dBc/Hz Phase Noise relative to carrier 155MHz @10kHz offset -125 dBc/Hz Phase Noise relative to carrier 155MHz @100kHz offset -123 dBc/Hz Note: Phase Noise measured at VIN = 0V 6. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Differential Voltage VOD 247 355 454 mV VDD Magnitude Change ∆VOD -50 50 mV Output High Voltage VOH 1.4 1.6 V Output Low Voltage VOL 0.9 1.1 V Offset Voltage VOS 1.125 1.2 1.375 V Offset Magnitude Change ∆VOS RL = 100 Ω (see figure) 0 3 25 mV Power-off Leakage IOXD Vout = VDD or GND VDD = 0V ±1 ±10 uA Output Short Circuit Current IOSD -5.7 -8 mA |
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