PLL130-09

High Speed Translator Buffer to LVDS

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 3

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Output Differential Voltage

247

355

454

mV

-50

50

mV

Output High Voltage

1.4

1.6

V

Output Low Voltage

0.9

1.1

V

Offset Voltage

1.125

1.2

1.375

V

Offset Magnitude Change

Ω

(see figure)

0

3

25

mV

Power-off Leakage

±1

±10

uA

Output Short Circuit Current

-5.7

-8

mA

4. LVDS Switching Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Differential Clock Rise Time

0.2

0.7

1.0

ns

Differential Clock Fall Time

Ω

(see figure)

0.2

0.7

1.0

ns

OUT

OUT

V

OD

V

OS

50

Ω

50

Ω

OUT

V

DIFF

R

C

C

LVDS Switching Test Circuit

LVDS Levels Test Circuit

LVDS Transistion Time Waveform

OUT

OUT

OUT

0V (Differential)

0V

20%

80%

20%

80%

t

R

t

F

V

DIFF