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PLL701-13 Datasheet(PDF) 4 Page - PhaseLink Corporation |
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PLL701-13 Datasheet(HTML) 4 Page - PhaseLink Corporation |
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4 / 5 page  PLL701-13 Low EMI Spread Spectrum Multiplier Clock 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/12/04 Page 4 3. TIMING CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Rise Time Tr Measured at 0.8V ~ 2.0V @ 3.3V 0.8 0.95 1.1 ns Fall Time Tf Measured at 2.0V ~ 0.8V @ 3.3V 0.78 0.85 0.9 ns Output Duty Cycle DT 45 50 55 % Input to Output Delay 2 4 ns Cycle to Cycle Jitter Tcyc-cyc Over output frequency range @ 3.3V 100 ps FUNCTIONAL DESCRIPTION Selectable spread spectrum and modulation rates The PLL701-13 provides selectable multiplication factor, as well as selectable modulation rate. Selection is made by connecting pins 2 (S2), 3 (S1), 4 (S0), and 7 (S3) to a logical “zero” or “one”, according to the output clock selection table on page 1. Default values for S(0:3) through internal pull-up and pull-down resistor Selection pins S0 and S3 have an internal pull-down resistor of 30k Ω, pins 2 and 3 (S1 and S2) have an internal pull-up resistor of 30k Ω. This internal pull-down (or pull-up) resistor will pull the input value to a logical “zero” (or “one” respectively) by default, i.e. when the pin is not connected to GND (VDD respectively). In order to override the internal pull-up (pull-down), the pin has to be connected to VDD (GND respectively). |
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