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PLL701-10 Datasheet(PDF) 1 Page - PhaseLink Corporation

Part No. PLL701-10
Description  Low EMI Spread Spectrum Multiplier IC (in Die or Package)
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Maker  PLL [PhaseLink Corporation]
Homepage  http://www.phaselink.com
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PLL701-10 Datasheet(HTML) 1 Page - PhaseLink Corporation

   
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PLL701-10
Low EMI Spread Spectrum Multiplier IC (in Die or Package)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
FEATURES
• Spread Spectrum Clock Generator/Multiplier with
output selectable from 1x to 8x.
• 13MHz to 240MHz output with output enable.
• 13MHz to 30 MHz reference input frequency
accepted from crystal or external clock signal.
• Reduced EMI from Spread Spectrum Modulation,
with selectable modulation amplitude for Center
Spread, Down Spread or Asymmetric Spread.
• TTL/CMOS compatible outputs.
• 3.3V Operating Voltage.
• 150 ps maximum cycle-to-cycle jitter.
• Available in 16-Pin 150mil SSOP or DIE.
DESCRIPTION
The PLL701-10 is a low EMI Clock Generator and
Multiplier for high-speed digital systems. It uses
Spread Spectrum Technology (SST) and permits
different levels of EMI reduction by selecting the
amplitude of the applied SST. The SST feature can
be turned off. An output enable input is also used.
The chip operates with input frequencies ranging from
13 to 30 MHz and provides 1x to 8x at its output.
OUTPUT CLOCK (FOUT) SELECTION
M2
M1
M0
FIN/XIN
(MHz)
Multiplier
FOUT
(MHz)
0
0
0
13 ~ 28
X1
13 ~ 28
0
0
1
13 ~ 28
X2
26 ~ 56
0
1
0
14 ~ 30
X3
42 ~ 90
0
1
1
13 ~ 28
X4
52 ~ 112
1
0
0
20 ~ 30
X5
100 ~ 150
1
0
1
17 ~ 30
X6
102 ~ 180
1
1
0
15 ~ 30
X7
105 ~ 210
1
1
1
13 ~ 28
X8
104 ~ 224
BLOCK DIAGRAM
PACKAGE PIN CONFIGURATION
DIE PAD CONFIGURATION
Note: ^: Internal pull-up resistor (120k
Ω for SD0, 30 kΩ for SC0-
SC2, SD1, M0-M2 and OE). The internal pull-up resistor
results in a default high value when no pull-down resistor is
connected to this pin.
*: SD0 and SD1 are latched upon power-up.
1
2
3
4
5
6
7
8
XIN/FIN
9
10
11
12
13
14
15
16
XOUT/SD0*^
M2^
M1^
M0^
SC0^
SC1^
SC2^
GND
AVDD
REF/SD1*^
VDD
SC3^
OE^
FOUT
GND
XIN/FIN = 10 ~ 30 MHz
XTAL
OSC
FOUT
XIN
XOUT
M(0:2)
SD(0:1)
SC(0:3)
PLL
SST
Control
Logic
OE
XOUT/SD0*^
GNDOSC
M2^
M1^
SC0^
M0^
SC1^
AVDD
AVDD
REF/SD1*^
VDD
VDD (optional)
VDD (optional)
SC3^
OE^
FOUT
GNDBUF
1
10
8
7
6
5
4
17
16
15
14
13
12
18
35
34
30
29
28
25
23
22
21
20
19
Y
X
69 mil
1700, 2540
C501A
A0404
-04A


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