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PLL701-05 Datasheet(PDF) 4 Page - PhaseLink Corporation |
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PLL701-05 Datasheet(HTML) 4 Page - PhaseLink Corporation |
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4 / 5 page 
Preliminary PLL701-05 Low EMI Spread Spectrum Multiplier Clock 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/26/02 Page 4 3. TIMING CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Rise Time Tr Measured at 0.8V ~ 2.0V @ 3.3V 0.8 0.95 1.1 ns Fall Time Tf Measured at 2.0V ~ 0.8V @ 3.3V 0.78 0.85 0.9 ns Output Duty Cycle DT 45 50 55 % Cycle to Cycle Jitter Tcyc-cyc FOUT=48MHz @ 3.3V 100 ps Cycle to Cycle Jitter Tcyc-cyc FOUT=72MHz @ 3.3V 100 ps INPUT LOGIC SELECTION THROUGH RESISTOR LOAD OPTION Register Power Up Reset Jumper options 27KOhm Strapping Resistor Clock Load S2 XIN EN R RB VDD RB 120Kohm XOUT |
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