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PLL701-01 Datasheet(PDF) 2 Page - PhaseLink Corporation

Part No. PLL701-01
Description  Low EMI Spread Spectrum Multiplier Clock
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Manufacturer  PLL [PhaseLink Corporation]
Direct Link  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PLL701-01 Datasheet(HTML) 2 Page - PhaseLink Corporation

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PLL701-01/02/04/06
Low EMI Spread Spectrum Multiplier Clock
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com
Rev 08/12/04 Page 2
BLOCK DIAGRAM
PIN DESCRIPTIONS
Name
Number
Type
Description
XIN/FIN
1
I
Crystal input to be connected to fundamental parallel mode crystal.(CL=18pF) or
clock input.
XOUT/SD
2
B
At power-up, this pin is an input pin to select modulation type. After input
sampling, this pin is crystal output. Has internal pull up resistor.
SC0
3
I
Digital control input to select modulation magnitude. Has internal pull-up.
SC1
4
I
Digital control input to select modulation magnitude. Has internal pull-up.
GND
5
P
Ground.
FOUT
6
O
Modulated Clock Frequency Output. The frequency before modulation is
synthesized by multiplying the input frequency by 1X, 2X, 4X, 6X depending on
the part number (PLL701-01, -02, -04, -06).
SC2
7
I
Digital control input to select modulation magnitude. Has internal pull-up.
VDD
8
P
Power Supply.
FUNCTIONAL DESCRIPTION
Selectable spread spectrum and modulation magnitudes
The PLL701-01/02/04/06 provides selectable spread spectrum modulation type, as well as selectable modulation
magnitude. Selection is made by connecting specific pins to a logical “zero” or “one” according to the output clock
selection table on page 1.
In order to reduce the number of pins on the chip, the PLL701-01/02/04/06 uses pin 2 (XOUT/SD) as a bi-
directional pin. The pin serves as modulation type selector input (SD) upon power-up (see output clock selection
table on page 1), and as XOUT crystal connection as soon as the input has been latched.
Pins 3 (SC0), 4 (SC1), and 7 (SC2) are used as inputs to select the spread spectrum modulation magnitude as
shown on the output clock selection table (page 1).
XTAL
OSC
FOUT
XIN/FIN
XOUT
SC(0:2)
PLL
SST
Control
Logic


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