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PLL601-03 Datasheet(PDF) 3 Page - PhaseLink Corporation

Part No. PLL601-03
Description  Low Phase Noise PLL Clock Multiplier
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Maker  PLL [PhaseLink Corporation]
Homepage  http://www.phaselink.com
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PLL601-03 Datasheet(HTML) 3 Page - PhaseLink Corporation

   
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Preliminary
PLL601-03
Low Phase Noise PLL Clock Multiplier
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/15/01 Page 3
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VCC
-0.5
7
V
Input Voltage Range
VI
-0.5
VCC
+0.5
V
Output Voltage Range
VO
-0.5
VCC
+0.5
V
Soldering Temperature
260
°C
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature
0
70
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
2. AC Specification
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input Frequency
Depends on selected multiplier
10
30
MHz
Output Frequency
At 3.3V
160
MHz
Output Rise Time
0.8V to 2.0V with no load
1.5
ns
Output Fall Time
2.0V to 0.8V with no load
1.5
ns
Duty Cycle
At VDD/2
45
50
55
%
Period jitter RMS
With capacitive decoupling
between VDD and GND
6.4
ps
Accumulated jitter RMS
With capacitive decoupling
between VDD and GND
9.4
ps
Phase Noise, relative to carrier, 155Mhz(x8)
100Hz offset, 3.3V
-103
dBc/Hz
Phase Noise, relative to carrier, 155Mhz(x8)
1kHz offset, 3.3V
-126
dBc/Hz
Phase Noise, relative to carrier, 155Mhz(x8)
10kHz offset, 3.3V
-133
dBc/Hz
Phase Noise, relative to carrier, 155Mhz(x8)
100kHz offset, 3.3V
-128
dBc/Hz


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