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PLL620-89 Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL620-89 Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 6 page PLL620-88/-89 Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 2 PIN AND PAD ASSIGNMENT Name Pin# Description VDD 1 Power Supply. XIN 2 Crystal input. See Crystal Specification on page 3. XOUT 3 Crystal output. See Crystal Specification on page 3. DNC 4 Do Not Connect. S2 5 Output Divide by Two selector pin. See the OUTPUT DIVIDE BY TWO SELECTOR Table on page 1. OE_CTRL 6 Output Enable input. See OUTPUT SELECTION AND ENABLE TABLE on page 1. DNC 8 Do Not Connect. GND 9 Ground. GNDBUF 10 Ground for output buffer circuitry. Q 11 PECL or LVDS output. VDDBUF 12 Power supply for output buffer circuitry. QBAR 13 Complementary PECL or LVDS output. GNDBUF 14 Ground for output buffer circuitry. DNC 15 Do Not Connect. DNC 16 Do Not Connect. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. |
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