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PLL702-06 Datasheet(PDF) 2 Page - PhaseLink Corporation

Part No. PLL702-06
Description  Clock Generator for Printer Applications
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Maker  PLL [PhaseLink Corporation]
Homepage  http://www.phaselink.com
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PLL702-06 Datasheet(HTML) 2 Page - PhaseLink Corporation

   
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PLL702-06
Clock Generator for Printer Applications
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
XIN
1
I
Crystal input to be connected to a 14.31818MHz fundamental crystal (CL =
20pF, parallel resonant mode). Load capacitors have been integrated on the
chip. No external Load capacitor is required.
XOUT
2
O
Crystal Output
VDDA
VDDD
GNDA
GNDD
3,4,11,12
P
3.3V power supply and GND.
VDDUSB
VDDCPU
GNDUSB
GNDCPU
5,6,8,10
P
CPU and USB outputs have separate power supply pins (VDD and GND).
VDDCPU can accept 3.3V and/or 2.5V power supply.
USB /
USB_SEL
7
B
Bi-directional pin. Upon power-on, the value of USB_SEL is latched in and used
to select the USB output (see USB selection table below). After the input has
been latched-in, the pin serves as USB (48, 30 or 12 MHz) output. 0=15k
Ω to
GND, M=leave open, 1=15k
Ω to VDD_USB
CPU
9
O
CPU clock signal output pin. The CPU clock frequency is selected as per the
frequency table on page 1, depending on the value of FS(0:1).
SS(0:1)
13,14
I
Bi-level input with internal Pull-up resistor for SST control (see Spread
Spectrum selection table on p.2). 0=connect to GND, 1=leave open (or to VDD).
FS(0:1)
15,16
I
Tri-level inputs for CPU clock frequency selection (see table on p.1). 0=connect
to GND, M=not connected, 1=connect to VDDA.
USB FREQUENCY TABLE
USB_SEL
USB
0
48 MHz
M
30 MHz
1
12 MHz
SPREAD SPECTRUM SELECTION TABLE
SS1
SS0
Spread Spectrum Modulation
0
0
OFF
0
1
- 0.50% – Down Spread
1
0
- 1.00% – Down Spread
1
1
- 1.25% – Down Spread


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