PRELIMINARY
CY7C0837V
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
Document #: 38-06059 Rev. *K
Page 6 of 28
Master Reset
The FLEx18 family devices undergo a complete reset by
taking its MRST input LOW. The MRST input can switch
asynchronously to the clocks. An MRST initializes the internal
burst counters to zero, and the counter mask registers to all
ones (completely unmasked). MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the FLEx18 family
devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CY7C0833V.
The highest memory location, 7FFFF is the mailbox for the
right port and 7FFFE is the mailbox for the left port. Table 2
shows that in order to set the INTR flag, a Write operation by
the left port to address 7FFFF will assert INTR LOW. At least
one byte has to be active for a Write to generate an interrupt.
A valid Read of the 7FFFF location by the right port will reset
INTR HIGH. At least one byte has to be active in order for a
Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to
is asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag
is set in a flow-thru mode (i.e., it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (i.e., it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Address Counter and Mask Register Operations[15]
This
section
describes
the
features
only
apply
to
512Kbit,1Mbit, 2Mbit, and 4Mbit devices. It does not apply to
9Mbit device. Each port of these devices has a programmable
burst address counter. The burst counter contains three
registers: a counter register, a mask register, and a mirror
register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset opera-
tions, and by the MRST. Table 3 summarizes the operation of
these registers and the required input control signals. The
MRST control signal is asynchronous. All the other control
signals in Table 3 (CNT/MSK, CNTRST, ADS, CNTEN) are
synchronized to the port’s CLK. All these counter and mask
operations are independent of the port’s chip enable inputs
(CE0 and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
s deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
i0s. A counter-mask register is used to control the counter
wrap.
Table 2. Interrupt Operation Example [1,11,12,13,14,16]
FUNCTION
LEFT PORT
RIGHT PORT
R/WL
CEL
A0L -
A18L
INTL
R/WR
CER
A0R -
A18R
INTR
Set Right INTR Flag
L
L
3FFFF
XXXX
L
Reset Right INTR Flag
X
XXX
H
L
3FFFF
H
Set Left INTL Flag
X
X
X
LLL
3FFFE
X
Reset Left INTL Flag
H
L
3FFFE
H
XXXX
Set Right INTR Flag
L
L
3FFFF
XXXX
L
Notes:
11. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the
CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
12. OE is “Don’t Care” for mailbox operation.
13. At least one of BE0, BE1 must be LOW.
14. A18x is a NC for CY7C0832V, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831V, therefore the Interrupt
addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830V, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x
and A15x are NC for CY7C0837V, therefore the Interrupt Addresses are 7FFF and 7FFE.
15. This section describes the CY7C0832V, CY7C0831V, CY7C0830V and CY7C0837V having 18, 17, 16 and 15 address bits.
16. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
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