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PLL601-02 Datasheet(PDF) 1 Page - PhaseLink Corporation

Part No. PLL601-02
Description  Low Phase Noise PLL Clock Multiplier
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Maker  PLL [PhaseLink Corporation]
Homepage  http://www.phaselink.com
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PLL601-02 Datasheet(HTML) 1 Page - PhaseLink Corporation

   
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PLL601-02
Low Phase Noise PLL Clock Multiplier
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
FEATURES
• Low phase noise XO
• Input from crystal or clock at 10-27MHz.
• Integrated crystal load capacitor: no external
load capacitor required.
• Output clocks up to 160MHz.
• Low phase noise (-125dBc/Hz @ 1kHz).
• Output Enable function.
• Low jitter (RMS): 6.4ps (period), 9.4ps (accum.)
• Advanced low power sub-micron CMOS process.
• 3.3V operation.
• Available in 16-Pin SOIC or TSSOP.
DESCRIPTION
The PLL601-02 is a low cost, high performance and
low phase noise clock synthesizer with 4x or 8x mul-
tiplier. Using PhaseLink’s proprietary analog and
digital Phase Locked Loop techniques, this IC can
produce up to a 160MHz out put. Ideal for
155.52MHz applications.
PIN CONFIGURATION
MULTIPLIER SELECT TABLE
S2
S1
S0
CLK
0
0
0
Test
0
0
1
Reserved
0
1
0
4x Input (Low Frequency VCO*)
0
1
1
8x Input (Low Frequency VCO*)
1
0
0
Reserved
1
0
1
XO Frequency Pass through
1
1
0
4x Input (High Frequency VCO*)
1
1
1
8x Input (High Frequency VCO*)
*: Low Frequency VCO is advised for best performance at 155.52MHz
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
CLK
9
10
11
12
13
14
15
16
REFEN
VDD
VDD
VDD
XOUT
S1^
XIN
GND
GND
GND
REFOUT
OE^
S0^
S2^
GND
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
ROM Based
Multipliers
VCO
Divider
XTAL
OSC
CLK
REFOUT
OE
REFEN
S2
S1
S0
XIN
XOUT


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