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PLL601-02 Datasheet(PDF) 3 Page - PhaseLink Corporation

Part No. PLL601-02
Description  Low Phase Noise PLL Clock Multiplier
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Maker  PLL [PhaseLink Corporation]
Homepage  http://www.phaselink.com
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PLL601-02 Datasheet(HTML) 3 Page - PhaseLink Corporation

   
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PLL601-02
Low Phase Noise PLL Clock Multiplier
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3
3. DC Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Operating Voltage
VDD
2.97
3.63
V
Input High Voltage
VIH
2
V
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
For XIN pin
(VDD/2)
+ 1
VDD/2
V
Input Low Voltage
VIL
For XIN pin
VDD/2
(VDD/2)
− 1
V
Output High Voltage
VOH
IOH = -25mA
2.4
V
Output Low Voltage
VOL
IOL = 25mA
0.4
V
Output High Voltage At
CMOS Level
VOH
IOH = -8mA
VDD-0.4
V
Operating Supply Current
IDD
No Load
35
mA
Short-circuit Current
IS
±50
mA
Input Capacitance
CIN
OE, Select Pins
5
pF
4. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
FXIN
Parallel Fundamental Mode
10
27
MHz
Crystal Loading Capacitance
Rating
CL (xtal)
15
pF
5. Jitter Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS
With capacitive decoupling
between VDD and GND
6.4
ps
Accumulated jitter RMS
With capacitive decoupling
between VDD and GND
9.4
ps
Phase Noise, relative to carrier, 155Mhz(x8)
100Hz offset, 3.3V
-103
dBc/Hz
Phase Noise, relative to carrier, 155Mhz(x8)
1kHz offset, 3.3V
-126
dBc/Hz
Phase Noise, relative to carrier, 155Mhz(x8)
10kHz offset, 3.3V
-133
dBc/Hz
Phase Noise, relative to carrier, 155Mhz(x8)
100kHz offset, 3.3V
-128
dBc/Hz


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