MAX1183 datasheet(3/9 Pages) MAXIM | Single-Ended or Fully Differential Signal Input Configuration

Part No.	MAX1183

Description	Single-Ended or Fully Differential Signal Input Configuration

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Manufacturer	MAXIM [Maxim Integrated Products]

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Note: Both input channels may be configured iden-

tically or differently.

5) Connect the logic analyzer to the square pin header

(J1). Channel A (Channel B) data is captured on J1-

1 (J1-23) through J1-19 (J1-41). If evaluating the

multiplexed ADC (MAX1185 or MAX1186), the out-

put data for Channel A and Channel B is captured

on a single 10-bit bus (J1-1 through J1-19) and the

A/B indicator signal can be monitored on J1-23 (see

Table 4 for bit locations and J1 header designators).

The system clock for both multiplexed and nonmulti-

plexed output operation is available on pin J1-43.

6) Connect a 3.0V, 300mA power supply to VA and

VADUT. Connect the ground terminal of this supply

to AGND.

7) Connect a 2.0V, 100mA power supply to VD and

VDDUT. Connect the ground terminal of this supply

to DGND.

8) Turn on both power supplies.

9) With a voltmeter, verify that 1.20V is measured

across test points TP1 and TP2. If the voltage is not

1.20V, adjust potentiometer R34 until 1.20V is

obtained.

10) Enable the function generators. Set the clock func-

tion generator for an output amplitude of 2.4VP-P

and frequency (fCLK)

≤ 80MHz. Set the analog input

signal generators for an output amplitude

≤ 2VP-P

and to the desired frequency. The two function gen-

erators should be phase-locked to each other.

11) Set the logic analyzer to capture on the clock’s rising

edge. In multiplexed output operation mode capture

Channel A data on the falling edge and Channel B

data on the rising edge of the logic analyzer clock.

12) Enable the logic analyzer.

13) Collect data using the logic analyzer.

Detailed Description

The MAX1181 EV kit is a fully-assembled and tested cir-

cuit board that contains all the components necessary to

evaluate the performance of the MAX1180, MAX1181,

MAX1182, MAX1183, MAX1184, MAX1185, MAX1186, or

MAX1190, dual 10-bit ADCs (Channel A and Channel B).

The MAX1180–MAX1184/MAX1190 dual outputs

(Channel A and Channel B) are nonmultiplexed and the

data is captured with two separate 10-bit buses. The

MAX1185 and MAX1186 dual outputs (Channel A and

Channel B) are multiplexed and data is captured with a

single 10-bit bus. The EV kit comes with the MAX1181

which can be evaluated with a maximum clock frequency

(fCLK) of 80MHz. The MAX1181 accepts differential or

single-ended analog input signals. With the proper board

configuration (as specified below), the ADC can be eval-

uated with both types of signals by supplying only one

single-ended analog signal to the EV kit.

The EV kit was designed as a four-layer PC board to

optimize the performance of the MAX1181. Separate

analog and digital power planes minimize noise cou-

pling between analog and digital signals. For simple

operation, the EV kit is specified to have 3.0V and 2.0V

DC power supplies applied to analog and digital power

planes, respectively. However, the digital plane can be

operated down to 1.7V without compromising the

board’s performance. The logic analyzer’s threshold

must be adjusted accordingly.

Access to Channel A and Channel B outputs is provid-

ed through connector J1. The 50-pin connector inter-

faces directly with a user-provided logic analyzer or

data acquisition system.

Power Supplies

The MAX1181 EV kit requires separate analog and digi-

tal power supplies for best performance. A 3.0V power

supply is used to power the analog portion of the

MAX1181 and the clock signal circuit. The MAX1181

analog supply voltage has a range of 2.7V to 3.6V, how-

ever, 3.0V must be supplied to the EV kit (VADUT, VA) to

meet the minimum input voltage supply to the clock

shaping circuit. A separate 2.0V power supply is used to

power the digital portion (VDDUT, VD) of the MAX1181

and the buffer/driver. It will operate with a voltage supply

as low as 1.7V and as high as 3.6V. Enhanced dynamic

performance is normally achieved when the digital sup-

ply voltage is lower than the analog supply voltage.

Clock

An on-board clock-shaping circuit generates a clock

signal from an AC sine-wave signal applied to the

CLOCK SMA connector. The input signal should not

exceed a magnitude of 2.6VP-P. The frequency of the

signal should not exceed 80MHz for the MAX1181. The

frequency of the sinusoidal input signal determines the

sampling frequency (fCLK) of the ADC. A differential line

receiver (U2) processes the input signal to generate the

CMOS clock signal. The signal’s duty cycle can be

adjusted with potentiometer R34. A clock signal with a

50% duty cycle (recommended) can be achieved by

adjusting R34 until 1.20V is produced across test points

TP1 and TP2, when the analog voltage supply is set to

3.0V (40% of the analog power supply). The clock signal

is available at the J1-J43 pin (CK), which can be used to

synchronize the output signal to the logic analyzer.

MAX1181 Evaluation Kit

_______________________________________________________________________________________

3

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