![]() |
Electronic Components Datasheet Search |
|
PLL601-15 Datasheet(PDF) 1 Page - PhaseLink Corporation |
|
PLL601-15 Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 5 page ![]() Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/08/02 Page 1 FEATURES • Full swing CMOS outputs with 25 mA drive capability at TTL levels. • Reference 20-30MHz crystal or clock. • Integrated crystal load capacitor: no external load capacitor required. • Output clocks up to 150MHz at 3.3V. • Low phase noise (-126dBc/Hz @ 1kHz). • Output Enable function. • Low jitter (RMS): 6.4ps (period), 9.4ps (accum.) • Advanced low power sub-micron CMOS process. • 3.3V operation. • Available in 8-Pin SOIC or TSSOP. DESCRIPTIONS The PLL601-15 is a low cost, high performance and low phase noise clock synthesizer. It implements PhaseLink’s proprietary analog and digital Phase Locked Loop techniques for a fixed 5x multiplier. The chip accepts crystal or clock inputs ranging from 20 to 30MHz, and produces outputs clocks up to 150MHz at 3.3V. BLOCK DIAGRAM PIN CONFIGURATION CRYSTAL RANGE Multiplier Xtal range 5x 20-30MHz Phase Locked Loop XTAL OSC CLK XIN XOUT 1 2 3 4 5 6 7 8 XIN GND GND GND XOUT VDD CLK VDD |