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PLL601-15 Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL601-15 Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 5 page ![]() Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/08/02 Page 2 PIN DESCRIPTIONS Name Number Type Description CLK 5 O Clock output from VCO. Equals the input frequency times multiplier. VDD 7,6 P 3.3V Power Supply. XIN 1 I Crystal input to be connected to 20-30MHz fundamental parallel mode crys- tal (CL=15pF). On chip load capacitors: No external capacitor required. XOUT 8 O Crystal Connection. GND 2, 3,4 P Ground. |