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XPC850DEZT80BU Datasheet(PDF) 11 Page - Motorola, Inc |
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XPC850DEZT80BU Datasheet(HTML) 11 Page - Motorola, Inc |
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11 / 76 page  MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 11 Layout Practices P D = PINT + PI/O P INT = IDD x VDD , watts—chip internal power P I/O = Power dissipation on input and output pins—user determined For most applications P I/O < 0.3 • PINT and can be neglected. If PI/O is neglected , an approximate relationship between P D and TJ is: P D = K ÷ (TJ + 273°C) (2) Solving equations (1) and (2) for K gives: K = P D • (TA + 273°C) + θJA • PD 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P D (at equilibrium) for a known T A . Using this value of K, the values of P D and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. 5.1 Layout Practices Each V CC pin on the MPC850 should be provided with a low-impedance path to the board’s supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The V CC power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip V CC and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as V CC and GND planes. All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the V CC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. |
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