THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

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4

ELECTRICAL CHARACTERISTICS

over recommended operating conditions, VREF = internal, fs = 6 MSPS, fI = 2 MHz at –1 dBFS (unless otherwise noted)

AC SPECIFICATIONS, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SINAD

Signal to noise ratio + distortion

Differential mode

56

59

dB

SINAD

Signal-to-noise ratio + distortion

Single-ended mode

55

58

dB

SNR

Signal to noise ratio

Differential mode

59

61

dB

SNR

Signal-to-noise ratio

Single-ended mode

58

60

dB

THD

Total harmonic distortion

Differential mode

–64

–61

dB

THD

Total harmonic distortion

Single-ended mode

–63

–60

dB

ENOB

Effective number of bits

Differential mode

9

9.5

Bits

ENOB

(SNR)

Effective number of bits

Single-ended mode

8.85

9.35

Bits

SFDR

Spurious free dynamic range

Differential mode

61

65

dB

SFDR

Spurious free dynamic range

Single-ended mode

60

64

dB

Analog Input

Full-power bandwidth with a source impedance of 150

Ω in

differential configuration.

Full scale sinewave, –3 dB

96

MHz

Full-power bandwidth with a source impedance of 150

Ω in

single-ended configuration.

Full scale sinewave, –3 dB

54

MHz

Small-signal bandwidth with a source impedance of 150

Ω in

differential configuration.

100 mVpp sinewave, –3 dB

96

MHz

Small-signal bandwidth with a source impedance of 150

Ω in

single-ended configuration.

100 mVpp sinewave, –3 dB

54

MHz

TIMING REQUIREMENTS

AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tpipe

Latency

5

CONV

CLK

tsu(CONV_CLKL-READL)

Setup time, CONV_CLK low before CS valid

10

ns

tsu(READH-CONV_CLKL)

Setup time, CS invalid to CONV_CLK low

20

ns

td(CONV_CLKL-SYNCL)

Delay time, CONV_CLK low to SYNC low

10

ns

td(CONV_CLKL-SYNCH)

Delay time, CONV_CLK low to SYNC high

10

ns