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PI3B16232V Datasheet(PDF) 3 Page - Pericom Semiconductor Corporation |
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PI3B16232V Datasheet(HTML) 3 Page - Pericom Semiconductor Corporation |
3 / 3 page 3 PS8178B 11/09/98 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI3B16232 3.3V, Synchronous 16-Bit to 32-Bit FET Mux/Demux BusSwitch Power Supply Characteristics Parameters Description Test Conditions (1) Min. Typ (2) Max. Units ICC Quiescent Power VCC = MAX.VIN = GND or VCC ——10 µA Supply Current ∆ICC Supply Current per VCC = MAX.VIN = 3.0 V (3) — — 750 µA Input @ TTL HIGH ICCD Supply Current per VCC = Max., — — 0.25 mA/ Input per MHz (4) A and B Pins Open MHz BE = GND Control Input Toggling 50% Duty Cycling Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for applicable device. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Per TTL driven input (control inputs only); A and B pins do not contribute to Icc. 4. This current applies to the control inputs only and represent the current required to switch internal capacitance at the specified frequency. The A and B inputs generate no significant AC or DC currents as they transition. This parameter is not tested, but is guaranteed by design. Switching Characteristics over Operating Range Notes: 1. See Test Circuits and Waveforms. 2. This parameter is guaranteed by design but not tested. 3. The bus switch contributes no propagational delay other than the RC delay of ON resistance of the switch and the load capacitance. r e t e m a r a Pn o it p i r c s e Ds n o it i d n o C t s e T ) 1 ( V 6 . 3 o t 0 . 3 = c c V s ti n U . n i M. x a M fCLK y c n e u q e r F k c o l C0 0 5 1z H M tW n o it a r u D e sl u Pw o l r o h g i h K L C3 . 3 s n ste m i T p u t e S K L C e r o f e b 1 S , 0 S ↑ 9 . 1 K L C e r o f e b N E K L C ↑ 9 . 1 h te m i T d l o H K L C r e tf a 1 S , 0 S ↑ 1 K L C r e tf a N E K L C ↑ 8 . 1 n e te m i T el b a n E2 B , 1 B o t K L C1 5 si d te m i T el b a si D2 B , 1 B o t K L C1 6 d p t 1 ) 3 , 2 ( n o it a g a p o r P y al e D B o t A5 2 . 0 d p t 2 n o it a g a p o r P y al e D A o t K L C1 5 . 4 |
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