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PDM31564
6
Rev. 1.2 - 3/31/98
PRELIMINARY
tAA
tRC
UB, LB
OE
CE
ADDRESSES
tOH
tAOE
tBA
DOUT
Output Data Valid
tLZBE(1)
tLZOE(1)
tLZCE(1)
tACE
tHZCE(1)
tHZOE(1)
tHZBE(1)
Read Timing Diagram
AC Electrical Characteristics
* VCC = 3.3V +5%
Description
-8*
-10*
–12
–15
–20
READ Cycle
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
READ cycle time
tRC
8
–
10
–
12—15—20—
ns
Address access time
tAA
–
8
–
10—12—15—20
ns
Chip enable access time
tACE
–
8
–
10—12—15—20
ns
Byte access time
tBA
–
5
–
6—7—8—9
ns
Output hold from address change
tOH
4–4–
4—4—4—
ns
Byte disable to output in low-Z(1)
tLZBE
0–0–
0—0—0—
ns
Byte enable to output in high-Z(1)
tHZBE
–
4
–
5—8—9—9
ns
Chip enable to output in low-Z(1)
tLZCE
3–3–
4—4—5—
ns
Chip disable to output high-Z(1, 2)
tHZCE
–
4
–
5—6—7—8
ns
Output enable access time
tAOE
–
4
–
5—6—7—
10
ns
Output enable to output in low-Z(1)
tLZOE
0–0–
0—0—0—
ns
Output disable to output in high-Z(1, 2)
tHZOE
–
4
–
5—5—6—6
ns
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