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DP8497 Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DP8497 Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 92 page  20 Pin Description (Continued) Symbol Pin Type Function DISK DATA CONTROLLER PINS RGATE 20 O READ GATE This active high output is asserted while the Disk Data Controller is reading data from the disk It commands an external data separator to acquire lock and enables the RDATA pin RCLK 21 I READ CLOCK This input is the disk data rate clock When RGATE is deasserted low this pin will receive the crystal or servo derived clock When RGATE is asserted high this pin will receive the recovered NRZ clock from the decoder Each rising edge of the clock at this input is used to strobe RDATA into the Disk Data Controller The AC timing characteristics should not be violated even during the time of transition between clock sources RDATA 22 I READ DATA This active high input accepts NRZ disk data from the data synchronizer decoder WGATE 23 O WRITE GATE This active high output is asserted while writing data to the disk WCLK 24 O WRITE CLOCK This output is derived from RCLK and is used to clock NRZ WDATA out from the DP84967 The rising edge indicates vaild WDATA WDATA 25 O WRITE DATA This active high output is the NRZ data to be written to the disk It is synchronized to WCLK It is held deasserted any time WGATE is deasserted INDEX 26 I INDEX This active high input from the disk drive signifies the start of a track Disk Data Controller commands may be synchronized to it AMFSEC 27 I ADDRESS MARK FOUNDSECTOR This active high input denotes the start of a sector in hard and pseudo-hard sectored drives Soft sectored drives use AMF to denote the start of header and data fields AME 28 O ADDRESS MARK ENABLE This active high output forces the read-channel encoder to generate an Address Mark It is also used to enable Address Mark detection for pseudo-hard sectored drives PROCESSOR INTERFACE PINS CRST 37 I RESET This active low Schmitt input will reset the DP84967 immediately without regard to data transfers which may be in progress Registers affected are listed in Table 31 PADB07 40 – 47 IO PROCESSORADDRESSDATA BUS 0 – 7 These eight active high bi-directional lines transfer information between the DP84967 and the processor ADSi 29 I ADDRESS STROBE IN This active high input latches the address from PADB0 – 7 on the falling edge The latched address is used to select internal registers RDi or DS 30 I The function of this pin is determined by the processor mode initialized by the RDY MODE pin READ STROBE (IN) NSCIntel mode This active low input combined with a low level on CS will assert data from the addressed register onto the PADB0 – 7 bus DATA STROBE ZilogMotorola Mode This active low input combined with a low level on CS will either assert data from the addressed register onto the PADB0 – 7 bus or it will write data present on the PADB0 – 7 bus into the register The data direction is determined by the WR pin WRi or 31 I The function of this pin is determined by the processor mode initialized by the RDYMODE pin RW WRITE STROBE (IN) NSCIntel Mode This active low input combined with a low level on CS will write data present on the PADB0 – 7 bus into the addressed register READWRITE ZilogMotorola Mode This pin determines the direction of data transfer on the PADB0 – 7 bus while the CS and DS pins are both asserted High e Read Low e Write CS 32 I CHIP SELECT This active low input must be asserted to access any of the registers 5 |
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