16 / 16 page
CY28419
Document #: 38-07444 Rev. *D
Page 16 of 16
Document History Page
Document Title: CY28419 Clock Synthesizer with Differential SRC and CPU Outputs
Document Number: 38-07444
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
121413
12/05/02
RGL
New Data Sheet
*A
127740
07/01/03
RGL
Added power-up requirements in the absolute maximum conditions table
*B
128452
07/30/03
RGL
Added 56 TSSOP package
*C
129785
10/03/03
RGL
Changed the voltage threshold on the single-ended output from 2.4V to 2.0V
and from 0.4V to 0.8V.
*D
203832
See ECN
RGL
Corrected Pin 37 from SRCT to SRCC.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
