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CY28419 Datasheet(PDF) 11 Page - Cypress Semiconductor

Part No. CY28419
Description  Clock Synthesizer with Differential SRC and CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28419 Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY28419
Document #: 38-07444 Rev. *D
Page 11 of 16
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–0.5
4.6
V
VDD_A
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to V SS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
0
70
°C
TJ
Temperature, Junction
Functional
150
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
15
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
45
°C/W
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
2000
V
UL-94
Flammability Rating
At 1/8 in.
V–0
MSL
Moisture Sensitivity Level
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
Parameter
Description
Conditions
Min.
Max.
Unit
VDD, VDD_A 3.3 Operating Voltage
3.3V ± 5%
3.135
3.465
V
VILI2C
Input Low Voltage
SDATA, SCLK
1.0
V
VIHI2C
Input High Voltage
SDATA, SCLK
2.2
V
VIL
Input Low Voltage
VSS – 0.5
0.8
V
VIH
Input High Voltage
2.0
VDD + 0.5
V
IIL
Input Leakage Current
except Pull-ups or Pull-downs 0 < VIN < VDD
–5
5
µA
IILI2C
Input High Voltage
SDATA, SCLK
2.2
V
VOL
Output Low Voltage
IOL = 1 mA
0.4
V
VOH
Output High Voltage
IOH = –1 mA
2.4
V
IOZ
High-impedance Output Current
–10
10
µA
CIN
Input Pin Capacitance
2
5
pF
COUT
Output Pin Capacitance
3
6
pF
LIN
Pin Inductance
–7
nH
VXIH
Xin High Voltage
0.7VDD
VDD
V
VXIL
Xin Low Voltage
0
0.3VDD
V
IDD
Dynamic Supply Current
At 200 MHz and all outputs loaded per Table 9
and Figure 7
280
mA
IPD
Power-down Supply Current
PD# asserted, Outputs Three-stated
1
mA
AC Electrical Specifications
Parameter
Description
Conditions
Min.
Max.
Unit
Crystal
TDC
XIN Duty Cycle
The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle
will not be within specification
47.5
52.5
%
TPERIOD
XIN Period
When XIN is driven from an external clock source 69.841
71.0
ns
TR / TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–10.0
ns
TCCJ
XIN Cycle-to-Cycle Jitter
As an average over 1-
µs duration
500
ps
LACC
Long-term Accuracy
Over 150 ms
300
ppm


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