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CY28419 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. CY28419
Description  Clock Synthesizer with Differential SRC and CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28419 Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY28419
Document #: 38-07444 Rev. *D
Page 6 of 16
Byte 3: Control Register 3
Bit @Pup
Name
Description
7
1
All PCI and SRC Clock outputs
except PCIF and SRC clocks
set to free-running
PCI_STP Control. 0 = SW PCI_STP not enabled and only the PCI_STP# pin will
stop the PCI stop enabled outputs, 1 = the PCI_STP function is enabled and the
stop enabled outputs will be stopped in a synchronous manner with no short pulses.
6
1
PCI6
PCI6 Output Enable
0 = Disabled, 1 = Enabled
5
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
USB_ 48MHz
USB_48 Drive Strength
0 = High drive strength, 1 = Normal drive strength
6
1
USB_ 48MHz
USB_48 Output Enable
0 = Disabled, 1 = Enabled
5
0
PCIF2
Allow control of PCIF2 with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
4
0
PCIF1
Allow control of PCIF1 with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
3
0
PCIF0
Allow control of PCIF0 with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
2
1
PCIF2
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
1
DOT_48
DOT_48 Output Enable
0 = Disabled, 1 = Enabled
6
1
CPUT3, CPUC3
0 = three-state, 1 = Enabled
5
0
3V66_4/VCH
VCH Select 66 MHz/48 MHz
0 = 3V66 mode, 1 = VCH (48MHz) mode
4
1
3V66_4/VCH
3V66_4/VCH Output Enable
0 = Disabled, 1 = Enabled
3
1
3V66_3
3V66_3 Output Enable
0 = Disabled, 1 = Enabled
2
1
3V66_2
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1
1
3V66_1
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
3V66_0
3V66_0 Output Enable
0 = Disabled, 1 = Enabled


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