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CY28419 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. CY28419
Description  Clock Synthesizer with Differential SRC and CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28419 Datasheet(HTML) 5 Page - Cypress Semiconductor

 
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CY28419
Document #: 38-07444 Rev. *D
Page 5 of 16
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
1
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
1
Reserved
Reserved
2
1
Reserved
Reserved
1
Externally
Selected
FS_B
FS_B reflects the value of the FS_B pin sampled on power-up.
0 = FS_B low at power-up
0
Externally
Selected
FS_A
FS_A reflects the value of the FS_A pin sampled on power-up.
0 = FS_A low at power-up
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
0
SRCT, SRCC
Allow control of SRCT/C with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
6
1
SRCT, SRCC
SRCT/C Output Enable
0 = Disabled (three-state), 1 = Enabled
5
1
Reserved
Reserved
4
1
Reserved
Reserved
3
1
Reserved
Reserved
2
1
CPUT2, CPUC2
CPUT/C2 Output Enable
0 = Disabled (three-state), 1 = Enabled
1
1
CPUT1, CPUC1
CPUT/C1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
0
1
CPUT0, CPUC0
CPUT/C0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
0
SRCT, SRCC
SRCT/C Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
6
0
SRCT, SRCC
SRCT/C Stop drive mode
0 = Driven in PCI_STP, 1 = Three-state in power-down
5
0
CPUT2, CPUC2
CPUT/C2 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
4
0
CPUT1, CPUC1
CPUT/C1 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
3
0
CPUT0, CPUC0
CPUT/C0 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved


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