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K6F2016U4D Datasheet(PDF) 5 Page - Samsung semiconductor

Part No. K6F2016U4D
Description  128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Download  9 Pages
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K6F2016U4D Datasheet(HTML) 5 Page - Samsung semiconductor

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Revision 1.0
CMOS SRAM
May 2000
K6F2016U4D Family
- 5 -
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product:TA=-40 to 85
°C)
1. The parameter is measured with 30pF test load.
Parameter List
Symbol
Speed Bins
Units
55ns1)
70ns
Min
Max
Min
Max
Read
Read Cycle Time
tRC
55
-
70
-
ns
Address Access Time
tAA
-
55
-
70
ns
Chip Select to Output
tCO
-
55
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
35
ns
UB, LB Access Time
tBA
-
55
-
70
ns
Chip Select to Low-Z Output
tLZ
10
-
10
-
ns
UB, LB Enable to Low-Z Output
tBLZ
10
-
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
5
-
ns
Chip Disable to High-Z Output
tHZ
0
20
0
25
ns
UB, LB Disable to High-Z Output
tBHZ
0
20
0
25
ns
Output Disable to High-Z Output
tOHZ
0
20
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write
Write Cycle Time
tWC
55
-
70
-
ns
Chip Select to End of Write
tCW
45
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
45
-
60
-
ns
UB, LB Valid to End of Write
tBW
45
-
60
-
ns
Write Pulse Width
tWP
40
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
20
ns
Data to Write Time Overlap
tDW
25
-
30
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
1. CS
≥Vcc-0.2V(CS controlled) or LB=UB≥Vcc-0.2V, CS≤0.2V(LB, UB controlled).
2. Super low power product=1
µA with special handling.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS
≥Vcc-0.2V1)
1.5
-
3.3
V
Data retention current
IDR
Vcc= 1.5V, CS
≥Vcc-0.2V1)
-
0.5
22)
µA
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=30pF+1TTL
CL1)
1. Including scope and jig capacitance
R22)
R12)
VTM3)
2. R1=3070
, R2=3150Ω
3. VTM =2.8V


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