8
D0308-214
Data Sheet
XE1203
4
GENERAL DESCRIPTION
The XE1203 is a direct conversion (Zero-IF) half-duplex data transceiver. It includes a receiver, a transmitter, a
frequency synthesizer and some service blocks. The circuit operates in three frequency ranges (433 MHz, 868MHz
and 915MHz) and uses 2-level FSK modulation. In a typical application, the XE1203 is programmed by a
microcontroller through the 3-wire serial bus SI, SO, SCK to write to and read from the configuration registers.
The XE1203 consists of 4 main functional blocks.
The receiver converts the incoming 2-level FSK modulated signal into a synchronized bit stream. The receiver is
composed of a low-noise amplifier, down-conversion mixers, base band filters, base band amplifiers, limiters,
demodulator and bit synchronizer. The bit synchronizer transforms the data output of the demodulator into a glitch-
free bit stream DATA and generates a synchronized clock DCLK to be used to sample the DATA signal easily
without loading an external processor with heavy signal processing. In addition, the receiver includes a Received
Signal Strength Indicator function (RSSI), a Frequency Error Indicator function (FEI) that gives indication about the
frequency error of the local oscillator, and pattern recognition function to detect programmable reference word in
the incoming bit stream. A user-selectable Barker coding/decoding block can be activated to spread the data with
an 11-bit Barker code upon transmission and decode the data upon reception by making a correlation between the
spread data and the same 11-bit Barker code. The bandwidth of the base-band filters, the frequency deviation of
the expected incoming FSK signal as well as the bit rate of this bit stream are programmable.
The transmitter performs the modulation of the carrier by an input bit stream and the transmission of the
modulated signal. The modulation is made directly through the frequency synthesizer. An on-chip power amplifier
then amplifies the signal. The output power is programmable among 4 possible values. The frequency deviation
and the bit rate for the transmit signal are the same as those programmed for the receiver section.
The frequency synthesizer generates the local oscillator (LO) signal for the receiver section as well as the FSK
modulated signal for the transmitter section. The core of the synthesizer is implemented with a Delta-Sigma PLL
architecture. The frequency is programmable with a step of 500 Hz in 3 frequency bands, 433-, 868-, and 915-
MHz. This section includes a crystal oscillator whose signal is the reference for the PLL. This reference frequency
can also be used as a reference clock for the external microcontroller through CLKOUT pin with a user selectable
division ratio of 4,8,16 or 32.
The control block generates the control signals according to the setting in its set of configuration registers.
The service block performs all the necessary functions for the circuit to work properly, including the internal voltage
and current sources.
4.1
DETAILED DESCRIPTION
4.1.1
Introduction
The pin DATA is used in both transmitter and receive sections and by default it is set to bidirectional mode. In
receiver mode, DATA holds the recovered information. In transmitter mode, the information to be sent applied to
this pin. If a unidirectional mode is required, the user has to set ADParam_disable_data_bidir to ‘1’. In this case,
pin DATA in an output mode used by receiver section and pin DATAIN is used for transmit data.
4.1.2
Receiver
The receiver section has two output signals indicating recovered clock (pin DCLK) and recovered NRZ data (pin
DATA). The bit synchronizer controls the recovered clock DCLK pin. If the bit synchronizer is enabled by setting
the bit “RTParam_Bitsync” to “1” the DCLK pin outputs the clock recovered from the incoming data stream.
Disabling bit synchronizer holds the DCLK pin at low level and connects the demodulator output to DATA pin.
The function of bit synchronizer is to remove the glitches from the bit stream DATA and to provide the synchronous
output clock at DCLK. The output DATA is valid at the rising edge of the DCLK.
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