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K7I643682M Datasheet(PDF) 4 Page - Samsung semiconductor

Part No. K7I643682M
Description  72Mb M-die DDRII SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant)
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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K7I643682M Datasheet(HTML) 4 Page - Samsung semiconductor

 
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2Mx36 & 4Mx18 DDRII CIO b2 SRAM
K7I643682M
K7I641882M
- 4 -
Rev 1.0
Aug. 2005
PIN CONFIGURATIONS(TOP VIEW) K7I643682M(2Mx36)
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb .
2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/SA*
SA
R/W
BW2
K
BW1
LD
SA
SA
CQ
B
NC
DQ27
DQ18
SA
BW3
KBW0
SA
NC
NC
DQ8
C
NC
NC
DQ28
VSS
SA
SA0
SA
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
SA
SA
SA
VSS
NC
NC
DQ10
P
NC
NC
DQ26
SA
SA
C
SA
SA
NC
DQ9
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
PIN NAME
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
SYMBOL
PIN NUMBERS
DESCRIPTION
NOTE
K, K
6B, 6A
Input Clock
C, C
6P, 6R
Input Clock for Output Data
1
CQ, CQ
11A, 1A
Output Echo Clock
Doff
1H
DLL Disable when low
SA0
6C
Burst Count Address Inputs
SA
3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
DQ0-35
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
Data Inputs Outputs
R/W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1,BW2, BW3
7B,7A,5A,5B
Block Write Control Pin,active when low
VREF
2H,10H
Input Reference Voltage
ZQ
11H
Output Driver Impedance Control Input
2
VDD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
VSS
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
Ground
TMS
10R
JTAG Test Mode Select
TDI
11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
NC
1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
No Connect
3


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