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IDT7290820PF Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT7290820PF Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 27 page 10 COMMERCIALTEMPERATURERANGE IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 TABLE 3 CONSTANT THROUGHPUT DELAY VALUE TABLE 4 INTERNAL REGISTER AND ADDRESS MEMORY MAPPING TABLE 2 VARIABLE THROUGHPUT DELAY VALUE Delay for Variable Throughput Delay Mode Input Rate (m – output channel number) (n – input channel number) m < n m = n, n+1, n+2 m > n+2 2.048 Mb/s 32 – (n-m) time-slots m-n + 32 time slots m-ntime-slots 4.096 Mb/s 64 – (n-m) time-slots m-n + 64 time-slots m-ntimeslots 8.192 Mb/s 128 – (n-m) time-slots m-n + 128 time-slots m-ntime-slots Delay for Constant Throughput Delay Mode Input Rate (m – output channel number) (n – input channel number) 2.048 Mb/s 32 + (32 – n) + m time-slots 4.096 Mb/s 64 + (64 – n) + m time-slots 8.192 Mb/s 128 + (128 – n) + m time-slots A7(1) A6 A5 A4 A3 A2 A1 A0 Location 0 000 0000 Control Register, CR 0 000 0001 Interface Mode Selection Register, IMS 0 000 0010 Frame Alignment Register, FAR 0 000 0011 Frame Input Offset Register 0, FOR0 0 000 0100 Frame Input Offset Register 1, FOR1 0 000 0101 Frame Input Offset Register 2, FOR2 0 000 0110 Frame Input Offset Register 3, FOR3 1 000 0000 Ch0 1 000 0001 Ch1 1 0 0 . .... . 1 001 1110 Ch30 1 001 1111 Ch31 (Note 2) 1 010 0000 Ch32 1 010 0001 Ch33 1 0 1 . .... . 1 011 1110 Ch62 1 011 1111 Ch63 (Note 3) 1 100 0000 Ch64 1 100 0001 Ch65 1 1 0 . .... . 1 111 1110 Ch126 1 111 1111 Ch127 (Note 4) Notes: 1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers. 2. Channels 0 to 31 are used when serial interface is at 2.048 Mb/s mode 3. Channels 0 to 63 are used when serial interface is at 4.096 Mb/s mode. 4. Channels 0 to 127 are used when serial interface is at 8.192 Mb/s mode. |
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