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SD60C52P Datasheet(PDF) 3 Page - AUK corp |
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SD60C52P Datasheet(HTML) 3 Page - AUK corp |
3 / 13 page KSI-W015-000 3 Pin Configuration Pin Description V CC : PIN 40 (DIP40), PIN 44 (PLCC 44) Supply voltage during normal, Idle and power down operations. V SS : PIN 20 (DIP 40), PIN 22 (PLCC 44) Circuit ground. Port 0 : PIN 32~39 (DIP 40), PIN 36~43 (PLCC44) Port 0 is an 8bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1's written to them float, and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullups when emitting 1's and source and sink several LS TTL inputs. Port 0 outputs the code bytes during program verification on the 60C52 external pullups resistors are required during program verification. Port 1 : PIN 1~8 (DIP 40), PIN 2~9 (PLCC44) Port 1 output buffers can drive LSI TTL inputs. Port 1 is an 8bit bi-directional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current because of the internal pullups SD60C32/P SD60C52/P 44PLCC 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 34 35 33 32 31 30 29 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 40DIP T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 INT0/P3.2 TxD/P3.1 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP PSEN ALE/PROG P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 |
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