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W320-03 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part No. W320-03
Description  200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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W320-03 Datasheet(HTML) 4 Page - Cypress Semiconductor

 
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W320-03
PRELIMINARY
Document #: 38-07248 Rev. **
Page 4 of 19
Serial Data Interface (SMBus)
To enhance the flexibility and function of the clock synthesizer,
a two signal SMBus interface is provided according to SMBus
specification. Through the Serial Data Interface, various de-
vice functions such as individual clock output buffers, etc can
be individually enabled or disabled. W320-03 support both
block read and block write operations.
The registers associated with the Serial Data Interface initial-
ize to their default setting upon power-up, and therefore use of
this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte, (most significant bit first) with the
ability to stop after any complete byte has been transferred.
Indexed bytes are not allowed.
A block write begins with a slave address and a WRITE con-
dition. The R/W bit is used by the SMBus controller as a data
direction bit. A zero indicates a WRITE condition to the clock
device. The slave receiver address is 11010010 (D2h).
A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the core
logic issues a byte count which describes number of additional
bytes required for the transfer, not including the command
code and byte count bytes. For example, if the host has 20 data
bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count byte is re-
quired to be a minimum of 1 byte and a maximum of 32 bytes
It may not be 0. Figure 1 shows an example of a block write.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Data Byte Configuration Map
Start
bit
Slave Address
1 1 0 1 0 0 1 0
R/W
0/1
A
Command
Code
0 0 0 0 0 0 0 0
AByte Count =
N
A
Data Byte 0
A
. . .
Data Byte N-1 AStop
bit
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Figure 1. An Example of a Block Write
From Master to Slave
From Slave to Master
Data Byte 0: Control Register (0 = Enable, 1 = Disable)
Bit
Affected
Pin#
Name
Description
Type
Power On
Default
Bit 7
5, 6, 7, 10,
11, 12, 13,
16, 17, 18,
33, 35
PCI [0:6]
CPU[2:0]
3V66[1:0]
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
R/W
0
Bit 6
--
TBD
TBD
R
0
Bit 5
35
3V66_1/VCH
VCH Select 66 MHz/48 MHz
0 = 66 MHz, 1 = 48 MHz
R/W
0
Bit 4
44, 45, 48,
49, 51, 52
CPU [2:0]
CPU# [2:0]
CPU_STOP#
Reflects the current value of the external CPU_STOP# pin
RN/A
Bit 3
10, 11, 12,
13, 16, 17,
18
PCI [6:0]
PCI_STOP#
(Does not affect PCI_F [2:0] pins)
R/W
N/A
Bit 2
--
--
S2
Reflects the value of the S2 pin sampled on Power-up
RN/A
Bit 1
--
--
S1
Reflects the value of the S1 pin sampled on Power-up
RN/A
Bit 0
--
--
S0
Reflects the value of the S1 pin sampled on Power-up
RN/A


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