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TSB42AC3PZT Datasheet(PDF) 11 Page - Texas Instruments

Part # TSB42AC3PZT
Description  General purpose link layer ideal for a wide-range of applications
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TSB42AC3PZT Datasheet(HTML) 11 Page - Texas Instruments

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1
SLLS593A—January 2006
TSB42AC3
2
Architecture
2.1
Function Block Diagram
The functional block diagram of the TSB42AC3 is shown in Figure 2−1.
Transmitter
Cycle Timer
Cycle Monitor
CRC
Receiver
Configuration Registers (CFR)
GRF
ITF
ATF
P
h
y
s
i
c
a
l
I
n
t
e
r
f
a
c
e
H
o
s
t
I
n
t
e
r
f
a
c
e
FIFO
Host
Processor
Serial
Bus
LINK CORE
ACK
Figure 2−1. Function Block Diagram
2.1.1 Physical Interface
The physical (PHY) interface provides PHY-level services to the transmitter and receiver. This includes gaining
access to the serial bus, sending packets, receiving packets, sending and receiving acknowledge packets,
and reading and writing PHY registers.
The PHY interface module also interfaces to the PHY chip and conforms to the PHY-link interface specification
described in Annex J of the IEEE 1394−1995 standard (see Section 7 of this document for more information).
2.1.2 Transmitter
The transmitter retrieves data from either the ATF or the ITF and creates correctly formatted serial-bus packets
to be transmitted through the PHY interface. When data is present at the ATF interface to the transmitter, the
TSB42AC3 PHY interface arbitrates for the serial bus immediately. When the data is present at the ITF
interface to the transmitter, the TSB42AC3 arbitrates for the serial bus during the next isochronous cycle. The
transmitter autonomously sends the cycle-start packets when the chip is a cycle master. The PHY interface
provides PHY-level services to the transmitter and receiver. This included gaining access to the serial bus,
sending packets, receiving packets, and sending and receiving acknowledge packets.


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