NT256D64S88AAG
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
(Part 1 of 2)
-7K
-75B
-8B
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Notes
tAC
DQ output access time from CK/CK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
1-4
tDQSCK
DQS output access time from CK/CK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
1-4
tCH
CK high-level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
1-4
tCL
CK low-level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
1-4
tCK
CL=2.5
7
12
7.5
12
8
12
ns
1-4
tCK
Clock cycle time
CL=2
7.5
12
10
12
10
12
ns
1-4
tDH
DQ and DM input hold time
0.5
0.5
0.6
ns
1-4,
15, 16
tDS
DQ and DM input setup time
0.5
0.5
0.6
ns
1-4,
15, 16
tDIPW
DQ and DM input pulse width (each input)
1.75
1.75
2
ns
1-4
tHZ
Data-out high-impedance time from CK/CK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
1-5
tLZ
Data-out low-impedance time from CK/CK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
1-5
tDQSQ
DQS-DQ skew (DQS & associated DQ
signals)
0.5
0.5
0.6
ns
1-4
tDQSQA
DQS-DQ skew (DQS & all DQ signals)
0.5
0.5
0.6
ns
1-4
tHP
Minimum half clk period for any given
cycle; defined by clk high(tCH )
or clk low (tCL ) time
tCH
or
tCL
tCH
or
tCL
tCH
or
tCL
tCK
1-4
tQH
Data output hold time from DQS
tHP -
0.75ns
tHP -
0.75ns
tHP -
1.0ns
tCK
1-4
tDQSS
Write command to 1st DQS latching
transition
0.75
1.25
0.75
1.25
0.75
1.25
tCK
1-4
tDQSL,H
DQS input low (high) pulse width
(write cycle)
0.35
0.35
0.35
tCK
1-4
tDSS
DQS falling edge to CK setup time
(write cycle)
0.2
0.2
0.2
tCK
1-4
tDSH
DQS falling edge hold time from CK
(write cycle)
0.2
0.2
0.2
tCK
1-4
tMRD
Mode register set command cycle time
14
15
16
ns
1-4
tWPRES
Write preamble setup time
0
0
0
ns
1-4, 7
tWPST
Write postamble
0.40
0.60
0.40
0.60
0.40
0.60
tCK
1-4, 6
tWPRE
Write preamble
0.25
0.25
0.25
tCK
1-4
tIH
Address and control input hold time
(fast slew rate)
0.9
1.1
1.1
ns
2-4, 9,
11, 12
tIS
Address and control input setup time
(fast slew rate)
0.9
1.1
1.1
ns
2-4, 9,
11, 12
tIH
Address and control input hold time
(slow slew rate)
1.0
1.1
1.1
ns
2-4,
10-12,
14
tIS
Address and control input setup time
(slow slew rate)
1.0
1.0
1.1
ns
2-4,
10-12,
14
REV 1.1
11
08/2002
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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