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R8830LV Datasheet(PDF) 11 Page - RDC Semiconductor

Part # R8830LV
Description  16-Bit Microcontroller with 8-bit external data bus
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Manufacturer  RDC [RDC Semiconductor]
Direct Link  http://www.rdc.com.tw/en/index.php
Logo RDC - RDC Semiconductor

R8830LV Datasheet(HTML) 11 Page - RDC Semiconductor

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RDC®
RISC DSP Controller
R8830LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
11
RST .
97
UZI /PIO26
Output/Input
Upper zero indicate. This pin is the logical OR of the inverted
A19-A16. It asserts in the T1 and is held throughout the cycle.
Chip Select Unit Interface
50
51
68
69
0
MCS /PIO14
1
MCS /PIO15
2
MCS /PIO24
3
MCS / RFSH /PIO25
Output/Input
Midrange memory chip selects. For MCS feature, these pins
are active low when enable the MMCS(A6h) register to access
a memory. The address ranges are programmable.
3
MCS -
0
MCS
are held high during bus hold. When
programming LMCS(A2h) register, pin69 is as a RFSH pin to
auto refresh the PSRAM.
57
UCS /
1
ONCE
Output/Input
Upper memory chip select/ONCE mode request 1. For UCS
feature, this pin acts low when system accesses the defined
portion memory block of the upper 512K bytes (80000h-
FFFFFh) memory region. UCS default acted address region is
from F0000h to FFFFFh after power-on reset. The address
range acting UCS is programmed by software. For
1
ONCE
feature. If
0
ONCE
and
1
ONCE
are sampled low on the
rising edge of RST . The microcontroller enters ONCE mode.
In ONCE mode, all pins are high-impedance. This pin
incorporates weakly pull-up resistor.
58
LCS /
0
ONCE
Output/Input
Lower memory chip select/ONCE mode request 0. For LCS
feature, this pin acts low when the microcontroller accesses the
defined portion memory block of the lower 512K (00000h-
7FFFFh) memory region. The address range acting LCS is
programmed by software.
For
0
ONCE feature, see UCS /
1
ONCE
description. This pin
incorporates weakly pull-up register.
59
60
6
PCS /A2/PIO2
5
PCS /A1/PIO3
Output/Input
Peripheral chip selects/latched address bit. For PCS feature,
these pins act low when the microcontroller accesses the fifth
or sixth region of the peripheral memory (I/O or memory
space). The base address of PCS is programmable. These pins
assert with the AD address bus and are not float during bus
hold.
For latched address bit feature. These pins output the latched
address A2, A1 when cleared the EX bit in the MCS and
PCS auxiliary register. The A2, A1 retains previous latched
data during bus hold.
62
63
65
66
3
PCS /
1
RTS /
1
RTR
/PIO19
2
PCS /
1
CTS /
1
ENRX PIO18
1
PCS /PIO17
0
PCS /PIO16
Output/Input
Peripheral chip selects. These pins act low when the
microcontroller accesses the defined memory area of the
peripheral memory block (I/O or memory address). For I/O
accessed, the base address can be programmed in the region
00000h to 0FFFFh.
For memory address access, the base address can be located in
the 1M byte memory address region. These pins assert with the
multiplexed AD address bus and are not float during bus hold.
Interrupt Control Unit Interface
47
NMI
Input
Nonmaskable Interrupt. The NMI is the highest priority
hardware interrupt and is nonmaskable. When this pin is
asserted (NMI transition from low to high), the microcontroller
always transfers the address bus to the location specified by the
nonmaskable interrupt vector in the microcontroller interrupt


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