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OR3T80 Datasheet(PDF) 59 Page - Agere Systems |
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OR3T80 Datasheet(HTML) 59 Page - Agere Systems |
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59 / 210 page  Lucent Technologies Inc. 59 Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) The external test (EXTEST) instruction allows the inter- connections between ICs in a system to be tested for opens and stuck-at faults. If an EXTEST instruction is performed for the system shown in Figure 36, the con- nections between U1 and U2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether the same value is seen at the other device. This is deter- mined by shifting 2 bits of data for each pin (one for the output value and one for the 3-state value) through the BSR until each one aligns to the appropriate pin. Then, based upon the value of the 3-state signal, either the I/O pad is driven to the value given in the BSR, or the BSR is updated with the input value from the I/O pad, which allows it to be shifted out TDO. The SAMPLE/PRELOAD instruction is useful for sys- tem debugging and fault diagnosis by allowing the data at the FPGA’s I/Os to be observed during normal operation or written during test operation. The data for all of the I/Os is captured simultaneously into the BSR, allowing them to be shifted-out TDO to the test host. Since each I/O buffer in the PICs is bidirectional, two pieces of data are captured for each I/O pad: the value at the I/O pad and the value of the 3-state control sig- nal. For preload operation, data is written from the BSR to all of the I/Os simultaneously. There are five ORCA-defined instructions. The PLC scan rings 1 and 2 (PSR1, PSR2) allow user-defined internal scan paths using the PLC latches/FFs. The RAM_Write Enable (RAM_W) instruction allows the user to serially configure the FPGA through TDI. The RAM_Read Enable (RAM_R) allows the user to read back RAM contents on TDO after configuration. The IDCODE instruction allows the user to capture a 32-bit identification code that is unique to each device and serially output it at TDO. The IDCODE format is shown in Table 14. Table 14. Boundary-Scan ID Code * PLC array size of FPGA, reverse bit order. Note: Table assumes version 0. Device Version (4 bits) Part* (10 bits) Family (6 bits) Manufacturer (11 bits) LSB (1 bit) OR3T20 0000 0011000000 110000 00000011101 1 OR3T30 0000 0111000000 110000 00000011101 1 OR3C/T55 0000 0100100000 110000 00000011101 1 OR3C/T80 0000 0110100000 110000 00000011101 1 OR3T125 0000 0011100000 110000 00000011101 1 OR3T165 0000 0000010000 110000 00000011101 1 |
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