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OR3T80 Datasheet(PDF) 74 Page - Agere Systems |
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OR3T80 Datasheet(HTML) 74 Page - Agere Systems |
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74 / 210 page  74 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) 5-5829(F) Figure 46. PCM Functional Block Diagram EXPRESSCLK FROM PROGRAMMABLE DIVIDER DIV0 REGISTER 7 REGISTER 6 REGISTER 5 REGISTER 4 REGISTER 3 REGISTER 2 REGISTER 1 REGISTER 0 FPGA-PCM INTERFACE COMBINATORIAL LOGIC PROGRAMMABLE DIVIDER DIV2 0 1 2 3 S4 0 1 2 3 S10 0 SYSTEM CLOCK OUTPUT EXPRESSCLK OUTPUT FROM EXPRESSCLK FEEDBACK FEEDBACK CLOCK PROGRAMMABLE DIVIDER DIV1 0 1 S2 PHASE DETECTOR PROGRAMMABLE DELAY LINES (32 TAPS) CHARGE PUMP AND LOW-PASS FILTER 1 0 S4 1...7 S5 1...7 1...7 1...7 S6 S7 S8 0 1 2 3 S4 0 1 2 3 S3 PCM INPUT CLOCK PAD ROUTING 0 1 2 3 S0 ROUTING |
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