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OR3C55 Datasheet(PDF) 19 Page - Agere Systems |
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OR3C55 Datasheet(HTML) 19 Page - Agere Systems |
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19 / 210 page  Lucent Technologies Inc. 19 Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Memory Mode The Series 3 PFU can be used to implement a 32 x 4 (128-bit) synchronous, dual-port random access memory (RAM). A block diagram of a PFU in memory mode is shown in Figure 9. This RAM can also be configured to work as a single-port memory and because initial values can be loaded into the RAM during configuration, it can also be used as a read-only memory (ROM). Figure 9. Memory Mode The PFU memory mode uses all LUTs and latches/FFs including the ninth FF in its implementation as shown in Figure 9. The read address is input at the KZ[3:0] and F5[A:D] inputs where KZ[0] is the LSB and F5[A:D] is the MSB, and the write address is input on CIN (MSB) and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write data is input on DIN[6, 4, 2, 0], where DIN[6] is the MSB, and read data is available combinatorially on F[6, 4, 2, 0] and registered on Q[6, 4, 2, 0] with F[6] and Q[6] being the MSB. The write enable signal is input at ASWE, and two write port enables are input on CE and LSR. The PFU CLK signal is used to synchronously write the data. The polarities of the clock, write enable, and port enables are all programmable. Write-port enables may be disabled if they are not to be used. 5-5969(F) Q6 Q4 Q2 Q0 D 5 Q CIN(WA4) KZ[3:0] 4 F5[A:D] D Q DIN7(WA3) D Q DIN5(WA2) D Q DIN3(WA1) D Q DIN1(WA0) D Q DIN6(WD3) D Q DIN4(WD2) D Q DIN2(WD1) D Q DIN0(WD0) D Q ASWE(WREN) EN S/R CE(WPE1) LSR(WPE2) CLK 4 WRITE WRITE READ READ 4 F6 F4 F2 F0 D Q D Q D Q D Q WRITE RAM CLOCK ADDRESS[4:0] ADDRESS[4:0] DATA[3:0] DATA[3:0] ENABLE |
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