Electronic Components Datasheet Search |
|
OR3C55 Datasheet(PDF) 92 Page - Agere Systems |
|
OR3C55 Datasheet(HTML) 92 Page - Agere Systems |
92 / 210 page 92 92 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes There are eight methods for configuring the FPGA. Seven of the configuration modes are selected on the M0, M1, and M2 inputs. The eighth configuration mode is accessed through the boundary-scan interface. A fourth input, M3, is used to select the frequency of the internal oscillator, which is the source for CCLK in some configuration modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz. The 1.25 MHz frequency is selected when the M3 input is unconnected or driven to a high state. There are three basic FPGA configuration modes: master, slave, and peripheral. The configuration data can be transmitted to the FPGA serially or in parallel bytes. As a master, the FPGA provides the control sig- nals out to strobe data in. As a slave device, a clock is generated externally and provided into the CCLK input. In the three peripheral modes, the FPGA acts as a microprocessor peripheral. Table 34 lists the functions of the configuration mode pins. Note that two configura- tion modes previously available on the OR2Cxx and OR2C/TxxA devices (master parallel down and syn- chronous peripheral) have been removed for Series 3 devices. Table 34. Configuration Modes * Motorola is a registered trademark of Motorola, Inc. Master Parallel Mode The master parallel configuration mode is generally used to interface to industry-standard, byte-wide mem- ory, such as the 2764 and larger EPROMs. Figure 54 provides the connections for master parallel mode. The FPGA outputs an 18-bit address on A[17:0] to memory and reads 1 byte of configuration data on the rising edge of RCLK. The parallel bytes are internally serial- ized starting with the least significant bit, D0. D[7:0] of the FPGA can be connected to D[7:0] of the micropro- cessor only if a standard prom file format is used. If a .bit or .rbt file is used from ORCA Foundry, then the user must mirror the bytes in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor. Figure 54. Master Parallel Configuration Schematic In master parallel mode, the starting memory address is 00000 Hex, and the FPGA increments the address for each byte loaded. One master mode FPGA can interface to the memory and provide configuration data on DOUT to additional FPGAs in a daisy-chain. The configuration data on DOUT is provided synchronously with the falling edge of CCLK. The frequency of the CCLK output is eight times that of RCLK. M2 M1 M0 CCLK Configuration Mode Data 0 0 0 Output Master Serial Serial 0 0 1 Input Slave Parallel Parallel 0 1 0 Output Microprocessor: Motorola* Pow- erPC Parallel 0 1 1 Output Microprocessor: Intel i960 Parallel 1 0 0 Output Master Parallel Parallel 101 Output Async Peripheral Parallel 110 Reserved 1 1 1 Input Slave Serial Serial EPROM A[17:0] DONE M2 M1 M0 HDC ORCA SERIES FPGA RCLK LDC VDD D[7:0] DOUT CCLK TO DAISY- CHAINED DEVICES VDD OR GND PRGM PROGRAM A[17:0] D[7:0] OE CE |
Similar Part No. - OR3C55 |
|
Similar Description - OR3C55 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |