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OR3T30 Datasheet(PDF) 67 Page - Agere Systems |
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OR3T30 Datasheet(HTML) 67 Page - Agere Systems |
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67 / 210 page  Lucent Technologies Inc. 67 Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) MPI Interface to FPGA The MPI interfaces to the user-programmable FPGA logic using a 4-bit address, read/write control signal, interrupt request signal, and user start and user end handshake signals. Timing numbers are provided so that the user-logic data transfers can be performed syn- chronously with the host processor ( PowerPC or i960) interface clock or asynchronously. Table 18 shows the internal interface signals between the MPI and the FPGA user-programmable logic. All of the signals are connected to the MPI in the upper-left corner of the device except for the D[7:0] and CLK signals that come directly from the I/O pin. The 4-bit addressing from the MPI to the PLCs allows for up to 16 locations to be addressed by the host pro- cessor. The user address space of the MPI does not address any hard register. Rather, the user is free to construct registers from FFs, latches, or RAM that can be selected by the addressing. Alternately, the decoded address signals may be used as control signals for other functions such as state machines or timers. The transaction sequence between the MPI and the user-logic is as follows. When the host processor ini- tiates a transaction as discussed in the preceding sec- tions, the MPI outputs the 4-bit user address (UA[3:0]) and the read/write control signal (URDWR, which is read-high, write-low regardless of host processor), and then asserts the user start signal, USTART. During a write from the host processor, the user logic can accept data written by the host processor from the D[7:0] pins once the USTART signal is asserted. The user logic ends a transaction by asserting an active-high user end (UEND) signal to the MPI. The MPI will insert wait-states in the host processor bus cycles, holding the host processor until the user- logic completes its task and returns a UEND signal, upon which the MPI generates an acknowledge signal. If the host processor is reading from the FPGA, the user logic must have the read data available on the D[7:0] pins of the FPGA when the UEND signal is asserted. If the user logic is fast or if the MPI user address is being decoded for use as a control signal, the MPI transaction time can be minimized by routing the USTART signal directly to the UEND input of the MPI . The timing section of this data sheet contains a parameter table with delay, setup, and hold timing requirements to operate the user-logic either synchro- nously or asynchronously with the MPI host interface clock. The user-logic may also assert an active-low interrupt request (UIRQ) to the MPI, which, in turn, asserts an interrupt to the host processor. Assertion of an inter- rupt request is asynchronous to the host processor clock and any read or write transaction occurring in the MPI . The user-logic is responsible for providing any required interrupt vectors for the host processor, and the user-logic must deassert the interrupt request once serviced. If the interrupt request is not deasserted in the user logic, it will continue to be asserted to the host processor via the MPI_IRQ pin. Table 18. MPI Internal Interface Signals Signal MPI I/O Function UA[3:0] O User Logic Address. Addresses up to 16 unique user registers or use as control signals. URDWRN O User Logic Read/Write Control Signal. High indicates a read from user logic by the host processor, low indicates a write to user-logic by the host processor. USTART O Active-High User Start Signal. Indicates the start of an MPI transaction between the host processor and the user logic. UEND I Active-High User End Signal. Indicates that the user-logic is finished with the current MPI transaction. UIRQ I Active-Low Interrupt. Sends request from the user-logic to the host processor. D[7:0] FPGA I/O User Data. Eight data bits come directly from the FPGA pins—not through the MPI . MPI_CLK FPGA I MPI Clock. The MPI clock is sourced by the host processor and comes directly from the FPGA pin—not through the MPI. |
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