Silego Technology Inc.
(408) 327-8800
SLGSSTVF16859H/V
7
PRELIMINARY
Data is subject to change.
May 28, 2003
Timing Requirements1:
(over recommended operating free-air temperature range, unless otherwise noted)
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of > 1V/ns.
3 - For data signal input slew rate of > 0.5V/ns and < 1V/ns.
4 - CLK, CLK signals input slew rate of > 1V/ns.
5 - Data input must be held low for a minimum time (tACT max) after RESET driven high
6 - Data and CLK,CLK inputs must be held at valid logic (high or low) levels for a minimum time
(tINACT max) after RESET driven low
Switching Characteristics:( For PC1600/2100/2700)
(over recommended operating free-air temperature range, unless otherwise noted)
Switching Characteristics:( For PC3200)
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD = 2.5V + 0.2V
UNITS
MIN
MAX
fclock
Clock frequency
210
MHz
tW
Pulse duration
CLK,CLK high or low
2.5
ns
tACT
Differential active time5
22
ns
tINACT Differential inactive time6
22
ns
tS
Setup time, fast slew rate2 & 4
Data before CLK
, CLK
0.65
ns
Setup time, slow slew rate3 & 4
0.75
ns
tH
Hold time, fast slew rate2 & 4
Data after CLK
, CLK
0.65
ns
Hold time, slow slew rate3 & 4
0.8
ns
SYMBOL
From
(Input)
To
(Output)
VDD = 2.5V + 0.2V
UNITS
MIN
TYP
MAX
fmax
210
MHz
tPD
CLK, CLK
Q
1.1
2.6
ns
tPDSS1 CLK, CLK
Q
1.1
2.9
ns
tPHL
RESET
Q
5
ns
SYMBOL
From
(Input)
To
(Output)
VDD = 2.6V + 0.1V
UNITS
MIN
TYP
MAX
fmax
210
MHz
tPD
CLK, CLK
Q
1.1
2.2
ns
tPDSS1 CLK, CLK
Q
1.1
2.48
ns
tPHL
RESET
Q
5
ns