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PDM31096
Rev. 2.4 - 5/27/98
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PRELIMINARY
Write Cycle No. 3 (Chip Enable Controlled)
AC Electrical Characteristics
* VCC = 3.3V +5%
NOTES: (For two previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured
±200 mV from steady state voltage.
2. At any given temperature and voltage condition, tHZCE is less than tLZCE.
3. This parameter is sampled.
4. WE is high for a READ cycle.
5. The device is continuously selected. All the Chip Enables are held in their active state.
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
Description
-8*
-10*
-12
-15
-20
WRITE Cycle
Sym
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
WRITE cycle time
tWC
8
—
10—12—15—20—
ns
Chip enable to end of write
tCW
8
—
10—10—11—13—
ns
Address valid to end of write
tAW
8
—
10—10—11—13—
ns
Address setup time
tAS
0—0—0—0—0—
ns
Address hold from end of write
tAH
0—0—0—0—0—
ns
Write pulse width
tWP
7—8—8—9—
10
—
ns
Data setup time
tDS
5—6—7—8—9—
ns
Data hold time
tDH
0—0—0—0—0—
ns
Write disable to output in low Z(1,3)
tLZWE
0—0—0—0—0—
ns
Write enable to output in high Z(1,3)
tHZWE
—4
5—6—7—9
ns
NOTE: Output Enable (OE) is inactive (high)
tWC
tAW
tWP
tCW
tAH
tAS
tDH
tDS
ADDR
CE
WE
DOUT
HIGH-Z
DIN
DATA VALID
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