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PRELIMINARY
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *B
Page 2 of 25
A0, A1, A
C
MODE
BWa
BWb
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQPa
DQPb
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
Sleep
Control
Logic Block Diagram–CY7C1356CV25 (512K x 18)
Selection Guide
CY7C1354CV25-225
CY7C1356CV25-225
CY7C1354CV25-200
CY7C1356CV25-200
CY7C1354CV25-167
CY7C1356CV25-167
Unit
Maximum Access Time
2.8
3.2
3.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
35
35
35
mA
Shaded areas contain advance information.Please contact your local Cypress sales representative for availability of these parts.
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.