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MP8799 Datasheet(PDF) 6 Page - Exar Corporation

Part No. MP8799
Description  CMOS Very Low Power, 1 MSPS, 10-Bit Analog-to-Digital Converter with 8-Channel Mux
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
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MP8799 Datasheet(HTML) 6 Page - Exar Corporation

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MP8799
6
Rev. 3.00
AUTO
BALANCE
CLOCK
DATA
ANALOG
INPUT
SAMPLE
N–1
Figure 1. MP8799 Timing Diagram
SAMPLE
N
SAMPLE
N+1
AUTO
BALANCE
N-1
TS
VIH
VIL
VOH
VOL
tF
tB
tR
tS
tDL
tHLD
THEORY OF OPERATION
Analog-to-Digital Conversion
The MP8799 converts analog voltages into 1024 digital
codes by encoding the outputs of 15 coarse and 67 fine compa-
rators. Digital logic is used to generate the overflow bit. The con-
version is synchronous with the clock and it is accomplished in 2
clock periods.
The reference resistance ladder is a series of 1025 resistors.
The first and the last resistor of the ladder are half the value of
the others so that the following relations apply:
RREF = 1024 R
VREF = VREF(+) – VREF(–) = 1024 LSB
The clock signal generates the two internal phases,
φ
B (CLK
high) and
φ
S (CLK low = sample) (See Figure 2.). The rising
edge of the CLK input marks the end of the sampling phase (
φ
S).
Internal delay of the clock circuitry will delay the actual instant
when
φ
S disconnects the latches from the comparators. This de-
lay is called aperture delay (tAP).
The coarse comparators make the first pass conversion and
selects a ladder range for the fine comparators. The fine compa-
rators are connected to the selected range during the next
φ
B
phase.
Figure 2. MP8799 Comparators
φS
B
φ
B
φ
S
φ
Latch
Ref
Ladder
COARSE COMPARATOR
S
S
B
B
φ
φ
φ
φ
Latch
Selected
Range
FINE COMPARATOR
VIN
VIN
VTAP
VTAP
AIN Sampling, Ladder Sampling, and Conversion Timing
Figure 3. shows this relationship as a timing chart. AIN sam-
pling, ladder sampling and output data relationships are shown
for the general case where the levels which drive the ladder
need to change for each sampled AIN time point. The ladder is
referenced for both last AIN sample and next AIN sample at the
same time. If the ladder’s levels change by more than 1 LSB,
one of the samples must be discarded. Also note that the clock
low period for the discarded AIN can be reduced to the minimum
tS time of 150 ns.
Figure 3. AIN Sampling, Ladder Sampling & Conversion Timing
Settle by Clock Update Time
Reference Stable Time – For Sample AIN1
Sample AIN1
Reference Stable Time – For Sample AIN2
Hold Reference Value Past
Clock Change for tAP Time
Short Cycle Sample will be discarded
Sample AIN2
AINX1
Not Used
AINX0
Sample AIN1AINX1
Sample AIN2
Sample Ladder
for AIN1
Sample Ladder
for AINX1
Sample Ladder
for AIN2
Sample Ladder
for AINX2
Compare Ladder
V/S AINX0
Compare Ladder
V/S AIN1
Compare Ladder
V/S AINX1
Compare Ladder
V/S AIN2
DATA AIN0
DATA AINX0
DATA AIN1
DATA AINX1
Not Used
Not Used
DATA
Ladder Compare
(LSB Bank)
Ladder Sample
Window (MSB Bank)
AIN Sample
Window
Clock
Update
References
External
Internal
External
tS
FB
FS
FB
FS
FB
FS


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