PRELIMINARY
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *B
Page 9 of 25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354CV25/CY7C1356CV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
part operates in accordance with IEEE Standard 1149.1-1900,
but doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
The
CY7C1354CV25/CY7C1356CV25
contains
a
TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Partial Write Cycle Description[2, 3, 4, 9]
Function (CY7C1354CV25)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write –No bytes written
L
H
H
H
H
Write Byte a– (DQa and DQPa)
L
HHH
L
Write Byte b – (DQb and DQPb)
LH
HLH
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
LHL
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
LL
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
LHLH
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Partial Write Cycle Description[2, 3, 4, 9]
Function (CY7C1356CV25)
WE
BWb
BWa
Read
Hx
x
Write – No Bytes Written
L
H
H
Write Byte a
− (DQ
a and DQPa)
LHL
Write Byte b – (DQb and DQPb)
LL
H
Write Both Bytes
L
L
L