Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1356CV25-200BZI Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1356CV25-200BZI
Description  9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
Download  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1356CV25-200BZI Datasheet(HTML) 9 Page - Cypress Semiconductor

Back Button CY7C1356CV25-200BZI Datasheet HTML 5Page - Cypress Semiconductor CY7C1356CV25-200BZI Datasheet HTML 6Page - Cypress Semiconductor CY7C1356CV25-200BZI Datasheet HTML 7Page - Cypress Semiconductor CY7C1356CV25-200BZI Datasheet HTML 8Page - Cypress Semiconductor CY7C1356CV25-200BZI Datasheet HTML 9Page - Cypress Semiconductor CY7C1356CV25-200BZI Datasheet HTML 10Page - Cypress Semiconductor CY7C1356CV25-200BZI Datasheet HTML 11Page - Cypress Semiconductor CY7C1356CV25-200BZI Datasheet HTML 12Page - Cypress Semiconductor CY7C1356CV25-200BZI Datasheet HTML 13Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 25 page
background image
PRELIMINARY
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *B
Page 9 of 25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354CV25/CY7C1356CV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
part operates in accordance with IEEE Standard 1149.1-1900,
but doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
The
CY7C1354CV25/CY7C1356CV25
contains
a
TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Partial Write Cycle Description[2, 3, 4, 9]
Function (CY7C1354CV25)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write –No bytes written
L
H
H
H
H
Write Byte a– (DQa and DQPa)
L
HHH
L
Write Byte b – (DQb and DQPb)
LH
HLH
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
LHL
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
LL
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
LHLH
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Partial Write Cycle Description[2, 3, 4, 9]
Function (CY7C1356CV25)
WE
BWb
BWa
Read
Hx
x
Write – No Bytes Written
L
H
H
Write Byte a
− (DQ
a and DQPa)
LHL
Write Byte b – (DQb and DQPb)
LL
H
Write Both Bytes
L
L
L


Similar Part No. - CY7C1356CV25-200BZI

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1356CV25-200BZI CYPRESS-CY7C1356CV25-200BZI Datasheet
492Kb / 28P
   9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL??Architecture
More results

Similar Description - CY7C1356CV25-200BZI

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1354DV25 CYPRESS-CY7C1354DV25 Datasheet
869Kb / 29P
   9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354CV25 CYPRESS-CY7C1354CV25_06 Datasheet
492Kb / 28P
   9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL??Architecture
CY7C1354C CYPRESS-CY7C1354C_06 Datasheet
516Kb / 28P
   9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL??Architecture
CY7C1354BV25 CYPRESS-CY7C1354BV25 Datasheet
518Kb / 27P
   256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture
CY7C1354A CYPRESS-CY7C1354A Datasheet
546Kb / 31P
   256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354A CYPRESS-CY7C1354A_04 Datasheet
402Kb / 28P
   256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture
CY7C1354B CYPRESS-CY7C1354B Datasheet
475Kb / 29P
   9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1370DV25 CYPRESS-CY7C1370DV25 Datasheet
421Kb / 30P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
CY7C1355C CYPRESS-CY7C1355C Datasheet
497Kb / 32P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C CYPRESS-CY7C1355C_06 Datasheet
504Kb / 28P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com