The data stream is clocked on the rising edge of LE into the DATA input MSB first The last two bits are the control bits DATA is

transferred into the counters as follows

Control Bits

DATA Location

C1

C2

0

0

N Counter

0

1

R Counter

1

X

F Latch

Programmable Divider (N Counters)

The N counter consists of the 6-bit swallow counter (A counter) and the 6-bit programmable counter (B counter) When the

control bits are ‘‘00’’ data is transferred from the 20-bit shift register into two 6-bit latches One latch sets the A counter while the

other sets the B counter MSB first Serial data format is shown below

LSB

MSB

C1

C2

N1

N2

N3

N4

N5

N6

N7

N8

N9

N10

N11

N12

X

X

X

X

X

X

Control Bits

Divide Ratio of Programmable Divider N

Don’t Care

6-Bit Swallow Counter Divide Ratio (A Counter)

Divide Ratio A

N6

N5

N4

N3

N2

N1

0

000000

1

000001

63

111111

Notes

Divide ratio 0 to 63

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