Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1361C-117AJXC Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C1361C-117AJXC
Description  9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Download  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1361C-117AJXC Datasheet(HTML) 7 Page - Cypress Semiconductor

Back Button CY7C1361C-117AJXC Datasheet HTML 3Page - Cypress Semiconductor CY7C1361C-117AJXC Datasheet HTML 4Page - Cypress Semiconductor CY7C1361C-117AJXC Datasheet HTML 5Page - Cypress Semiconductor CY7C1361C-117AJXC Datasheet HTML 6Page - Cypress Semiconductor CY7C1361C-117AJXC Datasheet HTML 7Page - Cypress Semiconductor CY7C1361C-117AJXC Datasheet HTML 8Page - Cypress Semiconductor CY7C1361C-117AJXC Datasheet HTML 9Page - Cypress Semiconductor CY7C1361C-117AJXC Datasheet HTML 10Page - Cypress Semiconductor CY7C1361C-117AJXC Datasheet HTML 11Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 30 page
background image
PRELIMINARY
CY7C1361C
CY7C1363C
Document #: 38-05541 Rev. *A
Page 7 of 30
Pin Definitions
Name
I/O
Description
A0, A1 , A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled
active. A[1:0] feed the 2-bit counter.
BWA,BWB
BWC,BWD
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is
HIGH.CE1 is sampled only when a new external address is loaded.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3[2]
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/ deselect the device.CE3 is sampled only when
a new external address is loaded.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automat-
ically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
ZZ
Input-
Asynchronous
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQPX are placed in a three-state
condition.The outputs are automatically three-stated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPX
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
During write sequences, DQPX is controlled by BWX correspondingly.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
VDD
Power Supply
Power supply inputs to the core of the device.
VDDQ
I/O Power Supply Power supply for the I/O circuitry.
VSS
Ground
Ground for the core of the device.


Similar Part No. - CY7C1361C-117AJXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1361C-100AJXC CYPRESS-CY7C1361C-100AJXC Datasheet
567Kb / 31P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361C-100AJXI CYPRESS-CY7C1361C-100AJXI Datasheet
567Kb / 31P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361C-100AXC CYPRESS-CY7C1361C-100AXC Datasheet
567Kb / 31P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361C-100AXC CYPRESS-CY7C1361C-100AXC Datasheet
1Mb / 32P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361C-100AXC CYPRESS-CY7C1361C-100AXC Datasheet
1Mb / 34P
   9-Mbit (256 K 횞 36/512 K 횞 18) Flow-Through SRAM
More results

Similar Description - CY7C1361C-117AJXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1361B CYPRESS-CY7C1361B Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361C CYPRESS-CY7C1361C_06 Datasheet
567Kb / 31P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361C CYPRESS-CY7C1361C_09 Datasheet
517Kb / 31P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361C_2009 CYPRESS-CY7C1361C_2009 Datasheet
1Mb / 32P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1355C CYPRESS-CY7C1355C Datasheet
497Kb / 32P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C CYPRESS-CY7C1355C_06 Datasheet
504Kb / 28P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture
CY7C1360 CYPRESS-CY7C1360 Datasheet
895Kb / 34P
   9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1360C CYPRESS-CY7C1360C Datasheet
423Kb / 31P
   9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1360C CYPRESS-CY7C1360C_06 Datasheet
521Kb / 31P
   9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1381CV25 CYPRESS-CY7C1381CV25 Datasheet
501Kb / 35P
   18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com