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MC68QH302PV20 Datasheet(PDF) 2 Page - Motorola, Inc |
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MC68QH302PV20 Datasheet(HTML) 2 Page - Motorola, Inc |
2 / 6 page 2 MC68QH302 Technical Summary MOTOROLA Figure 1. MC68QH302 Block Diagram The MC68QH302 supports a full ISDN basic rate interface with one serial channel left over to communicate with the DTE as shown in Figure 2. The dual-channel SCC1 is used to support the two B channels. Figure 2. MC68QH302 Supporting a Full ISDN Basic Rate Interface SCC1 (2 Channels) SCC2 + SCC3 SCP + 2 SMCs 1152 Bytes Dual-Ported RAM 8 DMA Channels RISC Controller Interrupt Controllers RAM + ROM 3 Timers 4 Chip Selects Parallel I/O General-Purpose DMA Channel M68000 Core Peripheral Bus 68000 System Bus 20 Address Lines 8/16 Data Lines MC68QH302 Flash + RAM + EEPROM MC145407 RS232-C MC68QH302 SCC2 SCC1* 145572 U-INTF or 145574 S/T INTF SCC3 IDL or GCI 2B + D Note: *SCC1 = Dual channel SCC, each channel used for a B channel X-FRMR and Line I/F |
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