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MC68QH302 Datasheet(PDF) 3 Page - Motorola, Inc

Part No. MC68QH302
Description  Quad HDLC Integrated Multiprotocol Processor
Download  6 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com

MC68QH302 Datasheet(HTML) 3 Page - Motorola, Inc

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MC68QH302 Technical Summary
The main features of the MC68QH302 are as follows (new features indicated in bold):
MC68000/MC68008 microprocessor core (may be disabled to use the IMP as a peripheral)
Serial interface block including:
— Independent direct memory access (IDMA) controller
— Interrupt controller with two modes of operation
— Parallel I/O ports, some with interrupt capability
— On-chip 1152 bytes of dual-ported RAM
— Three timers, including a software watchdog timer
— Four programmable chip-select lines with wait-state logic
— Programmable address mapping of dual-ported RAM and IMP registers
— On-chip clock generator with an output clock signal
— System control
– System control register
– Bus arbitration logic with low-interrupt latency support
– Hardware watchdog for monitoring bus activity
– Low power (standby) modes
– Disable CPU logic (M68000)
– Freeze control for debugging selected on-chip peripherals
– DRAM refresh controller
CP including:
— Main controller (RISC processor)
— Three physical full-duplex serial communication controllers (SCCs) with the following
– Totally transparent
– V.110
— SCC1 can support two logical HDLC or transparent channels running QH protocol
— Eight serial DMA channels dedicated to the four serial channels
— Capability to send /receive up to eight buffers/frames without M68000 core intervention
— Flexible physical interface accessible by SCCs for interchip digital link (IDL), general circuit
interface (GCI, also called IOM2), pulse code modulation (PCM), and nonmultiplexed serial
interface (NMSI) operation
— Serial communication port (SCP) for synchronous communication
— Serial management controllers (SMCs) for IDL and GCI channels
Application development system available with M68302FADS.

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