1

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT59920A

LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

SEPTEMBER 2001

2001

Integrated Device Technology, Inc.

DSC 5846/2

c

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Eight zero delay outputs

• Selectable positive or negative edge synchronization

• Synchronous output enable

• Output frequency: 15MHz to 100MHz

• CMOS outputs

• 3 skew grades:

• 3-level inputs for PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• Low Jitter: <200ps peak-to-peak

• Outputs drive 50

Ω

Ω

Ω

Ω

Ω terminated lines

• Pin-compatible with Cypress CY7B9920

• Available in SOIC package

FUNCTIONAL BLOCK DIAGRAM

G ND/sOE

REF

FS

PLL

FB

IDT59920A

LOW SKEW

PLL CLOCK DRIVER

TURBOCLOCK™ JR.

DESCRIPTION:

The IDT59920A is a high fanout phase lock loop clock driver in-

tended for high performance computing and data-communications appli-

cations. The IDT59920A has CMOS outputs.

The IDT59920A maintains Cypress CY7B9920 compatibility while

providing two additional features: Synchronous Output Enable (GND/

the GND/sOE pin is held low, all outputs are synchronously enabled

(CY7B9920 compatibility). However, if GND/sOE is held high, all out-

puts except Q2 and Q3 are synchronously disabled.

nized with the positive edge of the REF clock input (CY7B9920 compat-

negative edge of REF.

The FB signal is compared with the input REF signal at the phase

detector in order to drive the VCO. Phase differences cause the VCO of

the PLL to adjust upwards or downwards accordingly.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to

provide minimal jitter (or frequency variation) while still providing accu-

rate responses to input frequency changes.